This category includes topics related to floating-point computation.
The FPU (Floating Point Unit) handles floating-point calculations on 32-bit systems and the SSE (Streaming SIMD Extensions) handles floating-point calculations on 64-bit systems. You can prevent floating-point exceptions from occuring by using SetExceptionMask to mask some or all of them on both FPU and SSE. SetExceptionMask sets the floating-point exception bits in FPU Control Word and SSE's MXCSR Control/Status registers.
The FPU Control Word register is illustrated below:
- W1066 Lost Extended floating point precision. Reduced to Double (Object Pascal)
- Intel and Floating-Point
- x87 and SSE Floating Point Assists in IA-32: Flush-To-Zero (FTZ) and Denormals-Are-Zero (DAZ)
- Intel® 64 and IA-32 Architectures Software Developer's Manuals
- IA-64 Floating-Point Operations and the IEEE Standard for Binary Floating-Point Arithmetic
Pages in category "Floating-Point"
The following 17 pages are in this category, out of 17 total.